Demodulation block setting object. More...

Public Member Functions | |
| def | setup (self, float readout_frequency, float adc_sampling_interval, int num_adc_samples) |
| Generates the demodulator frequency word info. More... | |
Public Attributes | |
| frequency_word | |
| Demodulator frequency word. More... | |
| id | |
| Unique ID for demodulator block. More... | |
| num_cycles | |
| Number of FPGA clock cycles. More... | |
Demodulation block settings handler.
| setup | ( | self, | |
| float | readout_frequency, | ||
| float | adc_sampling_interval, | ||
| int | num_adc_samples | ||
| ) |
Generates the properly formatted frequency word information for the demodulator.
| [in] | readout_frequency | Rate at which the the ADC data is captured for demodulator calculation. |
| [in] | adc_sampling_interval | Current ADC sampling interval. |
| [in] | num_adc_samples | Number of ADC samples used for demodulator calculations. |
| frequency_word |
Object holding binary representation of angle step in half-pi steps.
| id |
Unique ID for demodulator block.
| num_cycles |
Number of FPGA clock cycles required to process the ADC samples during demodulation calculations.
Currently the ADC is 8x faster than FPGA. Hence every FPGA clock cycle, 8 ADC samples is available.